The present invention relates to digital test systems where the phase of a test signal is directly created by a variable clock output under control of an externally programmed input with respect to a reference signal and more particularly to a digital test system producing clock test signals in a plurality of channels, each controlled in phase with respect to a reference signal.
Digital test systems used for testing integrated circuits provide in a plurality of channel clock test signals to be applied to a plurality of points in the integrated circuit under test and it is important that each channel test signal be in a predetermined controlled phase relative to a reference clock signal. For example, when all the clock test signals are in phase with the reference, it is said that they have a common wave front without skew. The procedure followed to correct or eliminate skew is referred to as deskewing, inasmuch as any skew or tilt of the common wave front is corrected by the deskewing process. Heretofor, deskewing has required tedious hours of cable trimming and matching to bring all of the channel test signals into phase synchronism with the reference at the points where they are applied to the circuit under test. Furthermore, even after the channel test signals are deskewed, slight changes in circuit parameters that occur due to changing ambient conditions, and generally referred to as drift, will cause skewing to occur and, unless the drift is copensated for by deskewing, it will cause errors and decrease the reliability of the testing. It is one object of the present invention to provide a test system wherein deskewing can be accomplished relatively easily, as often as desired, even while the test system is in use testing an integrated circuit.
Once the test circuit is deskewed, it will provide a common wave front across the channel test signals to all inputs of the integrated circuit under test. In other words, the leading edges of all pulses from channel to channel at the points where they are applied to the integrated circuit under test will define a common wave front without any skew.
ln order to provide a test system with a wide dynamic range, it is desireable to provide a wave front of clock test signals that has a predetermined controlled skew that can be varied readily with respect to the reference. Clearly, this requires that each clock test signal be controlled in phase and compared to the reference. Furthermore, it is desireable to be able to change the skew of each clock test signal relative to the reference readily according to calibrated phase offset control signals and also to change the calibration from time to time. It is another object of the present invention to provide a test system with the capacity of controlling the skew of such clock test signals according to clock offset phase control signals and for varying the calibration of the offset control signal versus the phase offset of the corresponding clock signal over a relatively wide dynamic range.
It is another object of the present invention to provide a method of deskewing clock test signals automatically without resorting to cable trimming, matching etc.
It is another object to provide a method of controlling the skew of a clock signal with respect to a reference signal according to a phase offset control signal and for varying the calibration of the phase offset signal versus the phase offset of the clock relative to the reference.
According to a principle feature of the present invention, the phase offset of a clock test signal with respect to the reference signal is accomplished using a closed loop feedback circuit including a voltage controlled variable phase shifter for shifting phase of the clock signal, a phase comparator for comparing the shifted clock signal with the reference signal producing an output representative of the phase difference, a negatlve feedback circuit between the comparator output and the voltage control of the phase shifter and means in the feedback circuit for multiplying the comparator output feedback signal by the clock phase offset control signal, so that the clock phase offset is proportional to the offset control signal when the feedback system is in equilibrium. A preferred embodiment of the present invention includes the above described phase offset control with another feedback circuit and appropriate switching means for deskewing and for setting and changing the calibration of clock phase offset control versus the clock phase offset.
These and other objects and features of the present invention will be apparent from the following specific description of embodiments of the present invention taken in conjunction with the drawings.